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HM5164165F series hm5165165f series 64m edo dram (4-mword 16-bit) 8k refresh/4k refresh ade-203-1058b(z) rev. 2.0 nov. 30, 1999 description the hitachi HM5164165F series, hm5165165f series are 64m-bit dynamic rams organized as 4,194,304- word 16-bit. they have realized high performance and low power by employing cmos process technology. HM5164165F series, hm5165165f series offer extended data out (edo) page mode as a high speed access mode. they have the package variations of standard 50-pin plastic soj and standerd 50-pin plastic tsopii features single 3.3 v supply: 3.3 v 0.3 v access time: 50 ns/60 ns (max) power dissipation ? active: 432 mw/396 mw (max) (HM5164165F series) : 504 mw/432 mw (max) (hm5165165f series) ? standby : 1.8 mw (max) (cmos interface) : 1.1 mw (max) (l-version) edo page mode capability refresh cycles ? ras -only refresh 8192 cycles /64 ms (HM5164165F, HM5164165Fl) 4096 cycles /64 ms (hm5165165f, hm5165165fl) ? cbr/hidden refresh 4096 cycles /64 ms (HM5164165F, HM5164165Fl, hm5165165f, hm5165165fl)
HM5164165F series, hm5165165f series 2 4 variations of refresh ? ras -only refresh ? cas -before- ras refresh ? hidden refresh ? self refresh (l-version) 2 cas -byte control battery backup operation (l-version) ordering information type no. access time package HM5164165Fj-5 HM5164165Fj-6 50 ns 60 ns 400-mil 50-pin plastic soj (cp-50da) HM5164165Flj-5 HM5164165Flj-6 50 ns 60 ns hm5165165fj-5 hm5165165fj-6 50 ns 60 ns hm5165165flj-5 hm5165165flj-6 50 ns 60 ns HM5164165Ftt-5 HM5164165Ftt-6 50 ns 60 ns 400-mil 50-pin plastic tsop ii (ttp-50db) HM5164165Fltt-5 HM5164165Fltt-6 50 ns 60 ns hm5165165ftt-5 hm5165165ftt-6 50 ns 60 ns hm5165165fltt-5 hm5165165fltt-6 50 ns 60 ns
HM5164165F series, hm5165165f series 3 pin arrangement (HM5164165F series) v ss i/o15 i/o14 i/o13 i/o12 v ss i/o11 i/o10 i/o9 i/o8 nc v ss lcas ucas oe nc nc a12 a11 a10 a9 a8 a7 a6 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 v cc i/o0 i/o1 i/o2 i/o3 v cc i/o4 i/o5 i/o6 i/o7 nc v cc we ras nc nc nc nc a0 a1 a2 a3 a4 a5 v cc 50-pin tsop (top view) v ss i/o15 i/o14 i/o13 i/o12 v ss i/o11 i/o10 i/o9 i/o8 nc v ss lcas ucas oe nc nc a12 a11 a10 a9 a8 a7 a6 v ss v cc i/o0 i/o1 i/o2 i/o3 v cc i/o4 i/o5 i/o6 i/o7 nc v cc we ras nc nc nc nc a0 a1 a2 a3 a4 a5 v cc 50-pin soj (top view) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 pin description pin name function a0 to a12 address input ?row/refresh address a0 to a12 ?column address a0 to a8 i/o0 to i/o15 data input/output ras row address strobe ucas , lcas column address strobe we write enable oe output enable v cc power supply v ss ground nc no connection
HM5164165F series, hm5165165f series 4 pin arrangement (hm5165165f series) v ss i/o15 i/o14 i/o13 i/o12 v ss i/o11 i/o10 i/o9 i/o8 nc v ss lcas ucas oe nc nc nc a11 a10 a9 a8 a7 a6 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 v cc i/o0 i/o1 i/o2 i/o3 v cc i/o4 i/o5 i/o6 i/o7 nc v cc we ras nc nc nc nc a0 a1 a2 a3 a4 a5 v cc 50-pin tsop (top view) v ss i/o15 i/o14 i/o13 i/o12 v ss i/o11 i/o10 i/o9 i/o8 nc v ss lcas ucas oe nc nc nc a11 a10 a9 a8 a7 a6 v ss v cc i/o0 i/o1 i/o2 i/o3 v cc i/o4 i/o5 i/o6 i/o7 nc v cc we ras nc nc nc nc a0 a1 a2 a3 a4 a5 v cc 50-pin soj (top view) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 pin description pin name function a0 to a11 address input ?row/refresh address a0 to a11 ?column address a0 to a9 i/o0 to i/o15 data input/output ras row address strobe ucas , lcas column address strobe we write enable oe output enable v cc power supply v ss ground nc no connection
HM5164165F series, hm5165165f series 5 block diagram (HM5164165F series) a0 a1 to a8 a9 to a12 timing and control ras ucas lcas we oe column address buffers row address buffers i/o buffers i/o0 to i/o15 column decoder row decoder 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array
HM5164165F series, hm5165165f series 6 block diagram (hm5165165f series) a0 a1 to a9 timing and control ras ucas lcas we oe column address buffers row address buffers i/o buffers i/o0 to i/o15 column decoder row decoder 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array 4m array a10 a11
HM5164165F series, hm5165165f series 7 operation table ras lcas ucas we oe i/o 0 to i/o 7 i/o 8 to i/o 15 operation h high-z high-z standby l l h h l dout high-z read cycle l h l h l high-z dout lllhl dout dout llhl* 2 din early write cycle lhll* 2 din llll* 2 din din llhl* 2 h din delayed write cycle lhll* 2 h din llll* 2 h din din l l h h to l l to h dout/din high-z read-modify-write cycle l h l h to l l to h high-z dout/din lllh to ll to h dout/din dout/din lhh high-z high-z ras -only refresh cycle h to l h l h high-z high-z cas -before- ras refresh cycle or h to l l h h high-z high-z self refresh cycle (l-version) h to l l l h high-z high-z l l l h h high-z high-z read cycle (output disabled) notes: 1. h: v ih (inactive) l: v il (active) : v ih or v il 2. t wcs 3 0 ns: early write cycle t wcs < 0 ns: delayed write cycle 3. mode is determined by the or function of the ucas and lcas . (mode is set by the earliest of ucas and lcas active edge and reset by the latest of ucas and lcas inactive edge.) however write operation and output high-z control are done independently by each ucas , lcas . ex. if ras = h to l, lcas = l, ucas = h, then cas -before- ras refresh cycle is selected.
HM5164165F series, hm5165165f series 8 absolute maximum ratings parameter symbol value unit terminal voltage on any pin relative to v ss v t ?.5 to v cc + 0.5 ( 4.6 v (max)) v power supply voltage relative to v ss v cc ?.5 to +4.6 v short circuit output current iout 50 ma power dissipation p t 1.0 w storage temperature tstg ?5 to +125 c dc operating conditions parameter symbol min typ max unit notes supply voltage v cc 3.0 3.3 3.6 v 1, 2 v ss 000 v2 input high voltage v ih 2.0 v cc + 0.3 v 1 input low voltage v il ?.3 0.8 v 1 ambient temperature range ta 0 70 ?c notes: 1. all voltage referred to v ss . 2. the supply voltage with all v cc pins must be on the same level. the supply voltage with all v ss pins must be on the same level.
HM5164165F series, hm5165165f series 9 dc characteristics (HM5164165F series) HM5164165F -5 -6 parameter symbol min max min max unit test conditions operating current* 1, * 2 i cc1 120 110 ma t rc = min standby current i cc2 2 2 ma ttl interface ras , ucas , lcas = v ih dout = high-z 0.5 0.5 ma cmos interface ras , ucas , lcas 3 v cc ?0.2 v dout = high-z standby current (l-version) i cc2 300 300 m a cmos interface ras , ucas , lcas 3 v cc ?0.2 v dout = high-z ras -only refresh current* 2 i cc3 120 110 ma t rc = min standby current* 1 i cc5 ? 5 ma ras = v ih ucas , lcas = v il dout = enable cas -before- ras refresh current i cc6 120 110 ma t rc = min edo page mode current* 1, * 3 i cc7 120 110 ma ras = v il , cas cycle, t hpc = t hpc min battery backup current* 4 (standby with cbr refresh) (l-version) i cc10 1.2 1.2 ma cmos interface dout = high-z cbr refresh: t rc = 15.6 m s t ras 0.3 m s self refresh mode current (l-version) i cc11 500 500 m a cmos interface ras , ucas , lcas 0.2 v dout = high-z input leakage current i li ? 5 5 5 m a 0 v vin v cc + 0.3 v output leakage current i lo ? 5 5 5 m a 0 v vout v cc dout = disable output high voltage v oh 2.4 v cc 2.4 v cc v high iout = ? ma output low voltage v ol 0 0.4 0 0.4 v low iout = 2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. measured with one sequential address change per edo cycle, t hpc . 4. v ih 3 v cc ?0.2 v, 0 v v il 0.2 v.
HM5164165F series, hm5165165f series 10 dc characteristics (hm5165165f series) hm5165165f -5 -6 parameter symbol min max min max unit test conditions operating current* 1, * 2 i cc1 140 120 ma t rc = min standby current i cc2 2 2 ma ttl interface ras , ucas , lcas = v ih dout = high-z 0.5 0.5 ma cmos interface ras , ucas , lcas 3 v cc ?0.2 v dout = high-z standby current (l-version) i cc2 300 300 m a cmos interface ras , ucas , lcas 3 v cc ?0.2 v dout = high-z ras -only refresh current* 2 i cc3 140 120 ma t rc = min standby current* 1 i cc5 ? 5 ma ras = v ih ucas , lcas = v il dout = enable cas -before- ras refresh current i cc6 140 120 ma t rc = min edo page mode current* 1, * 3 i cc7 120 110 ma ras = v il , cas cycle, t hpc = t hpc min battery backup current* 4 (standby with cbr refresh) (l-version) i cc10 1.2 1.2 ma cmos interface dout = high-z cbr refresh: t rc = 15.6 m s t ras 0.3 m s self refresh mode current (l-version) i cc11 500 500 m a cmos interface ras , ucas , lcas 0.2 v dout = high-z input leakage current i li ? 5 5 5 m a 0 v vin v cc + 0.3 v output leakage current i lo ? 5 5 5 m a 0 v vout v cc dout = disable output high voltage v oh 2.4 v cc 2.4 v cc v high iout = ? ma output low voltage v ol 0 0.4 0 0.4 v low iout = 2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. measured with one sequential address change per edo cycle, t hpc . 4. v ih 3 v cc ?0.2 v, 0 v v il 0.2 v.
HM5164165F series, hm5165165f series 11 capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) parameter symbol min typ max unit notes input capacitance (address) c i1 5 pf1 input capacitance (clocks) c i2 7 pf1 output capacitance (data-in, data-out) c i/o 7 pf 1, 2 notes : 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. ras , ucas and lcas = v ih to disable dout.
HM5164165F series, hm5165165f series 12 ac characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v)* 1, * 2, * 19, * 26 test conditions ? input rise and fall time: 2 ns ? input pulse levels: v il = 0 v, v ih = 3.0 v ? input timing reference levels: 0.8 v, 2.0 v ? output timing reference levels: 0.8 v, 2.0 v ? output load: 1 ttl gate + c l (100 pf) (including scope and jig) read, write, read-modify-write and refresh cycles (common parameters) HM5164165F/hm5165165f -5 -6 parameter symbol min max min max unit notes random read or write cycle time t rc 84 104 ns ras precharge time t rp 30 40 ns cas precharge time t cp 8 10 ns 30 ras pulse width t ras 50 10000 60 10000 ns cas pulse width t cas 8 10000 10 10000 ns row address setup time t asr 00 ns row address hold time t rah 8 10 ns column address setup time t asc 0 0 ns 27 column address hold time t cah 8 10 ns 27 ras to cas delay time t rcd 12 37 14 45 ns 3 ras to column address delay time t rad 10 25 12 30 ns 4 ras hold time t rsh 13 15 ns cas hold time t csh 35 40 ns cas to ras precharge time t crp 5 5 ns 28 oe to din delay time t oed 13 15 ns 5 oe delay time from din t dzo 0 0 ns 6 cas delay time from din t dzc 0 0 ns 6 transition time (rise and fall) t t 2 50 2 50 ns 7
HM5164165F series, hm5165165f series 13 read cycle HM5164165F/hm5165165f -5 -6 parameter symbol min max min max unit notes access time from ras t rac 50 60 ns 8, 9 access time from cas t cac 13 15 ns 9, 10, 17 access time from address t aa 25 30 ns 9, 11, 17 access time from oe t oea 13 15 ns 9 read command setup time t rcs 0 0 ns 27 read command hold time to cas t rch 0 0 ns 12, 28 read command hold time from ras t rchr 50 60 ns read command hold time to ras t rrh 0 0 ns 12 column address to ras lead time t ral 25 30 ns column address to cas lead time t cal 15 18 ns cas to output in low-z t clz 00 ns output data hold time t oh 3 3 ns 21 output data hold time from oe t oho 33 ns output buffer turn-off time t off 13 15 ns 13, 21 output buffer turn-off to oe t oez 13 15 ns 13 cas to din delay time t cdd 13 15 ns 5 output data hold time from ras t ohr 3 3 ns 21 output buffer turn-off to ras t ofr 13 15 ns 13, 21 output buffer turn-off to we t wez 13 15 ns 13 we to din delay time t wed 13 15 ns ras to din delay time t rdd 13 15 ns
HM5164165F series, hm5165165f series 14 write cycle HM5164165F/hm5165165f -5 -6 parameter symbol min max min max unit notes write command setup time t wcs 0 0 ns 14, 27 write command hold time t wch 8 10 ns 27 write command pulse width t wp 8 10 ns write command to ras lead time t rwl 13 15 ns write command to cas lead time t cwl 8 10 ns 29 data-in setup time t ds 0 0 ns 15, 29 data-in hold time t dh 8 10 ns 15, 29 read-modify-write cycle HM5164165F/hm5165165f -5 -6 parameter symbol min max min max unit notes read-modify-write cycle time t rwc 116 140 ns ras to we delay time t rwd 67 79 ns 14 cas to we delay time t cwd 30 34 ns 14 column address to we delay time t awd 42 49 ns 14 oe hold time from we t oeh 13 15 ns refresh cycle HM5164165F/hm5165165f -5 -6 parameter symbol min max min max unit notes cas setup time (cbr refresh cycle) t csr 5 5 ns 27 cas hold time (cbr refresh cycle) t chr 8 10 ns 28 we setup time (cbr refresh cycle) t wrp 00 ns we hold time (cbr refresh cycle) t wrh 8 10 ns ras precharge to cas hold time t rpc 5 5 ns 27
HM5164165F series, hm5165165f series 15 edo page mode cycle HM5164165F/hm5165165f -5 -6 parameter symbol min max min max unit notes edo page mode cycle time t hpc 20 25 ns 20 edo page mode ras pulse width t rasp 100000 100000 ns 16 access time from cas precharge t cpa 28 35 ns 9, 17, 28 ras hold time from cas precharge t cprh 28 35 ns output data hold time from cas low t doh 3 3 ns 9, 22 cas hold time referred oe t col 8 10 ns cas to oe setup time t cop 55 ns read command hold time from cas precharge t rchc 28 35 ns write pulse width during cas precharge t wpe 8 10 ns oe precharge time t oep 8 10 ns edo page mode read-modify-write cycle HM5164165F/hm5165165f -5 -6 parameter symbol min max min max unit notes edo page mode read-modify-write cycle time t hprwc 57 68 ns we delay time from cas precharge t cpw 45 54 ns 14, 28 refresh (HM5164165F series) parameter symbol max unit note refresh period t ref 64 ms 8192 cycles
HM5164165F series, hm5165165f series 16 refresh (hm5165165f series) parameter symbol max unit note refresh period t ref 64 ms 4096 cycles self refresh mode (l-version) HM5164165Fl/hm5165165fl -5 -6 parameter symbol min max min max unit notes ras pulse width (self refresh) t rass 100 100 m s25 ras precharge time (self refresh) t rps 90 110 ns 25 cas hold time (self refresh) t chs ?0 ?0 ns 29 notes: 1. ac measurements assume t t = 2 ns. 2. an initial pause of 200 m s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras -only refresh or cas -before- ras refresh). 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, than the access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. either t oed or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 9. measured with a load circuit equivalent to 1 ttl loads and 100 pf. 10. assumes that t rcd 3 t rcd (max) and t rcd + t cac (max) 3 t rad + t aa (max). 11. assumes that t rad 3 t rad (max) and t rcd + t cac (max) t rad + t aa (max). 12. either t rch or t rrh must be satisfied for a read cycles. 13. t off (max), t oez (max), t wez (max) and t ofr (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), and t awd 3 t awd (min), or t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t ds and t dh are referred to ucas and lcas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles.
HM5164165F series, hm5165165f series 17 16. t rasp defines ras pulse width in edo page mode cycles. 17. access time is determined by the longest among t aa , t cac and t cpa . 18. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. 19. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc /v ss line noise, which causes to degrade v ih min/v il max level. 20. t hpc (min) can be achieved during a series of edo page mode write cycles or edo page mode read cycles. if both write and read operation are mixed in a edo page mode ras cycle (edo page mode mix cycle (1), (2)), minimum value of cas cycle (t cas + t cp + 2 t t ) becomes greater than the specified t hpc (min) value.the value of cas cycle time of mixed edo page mode is shown in edo page mode mix cycle (1) and (2). 21. data output turns off and becomes high impedance from later rising edge of ras and cas . hold time and turn off time are specified by the timing specifications of later rising edge of ras and cas between t ohr and t oh , and between t ofr and t off . 22. t doh defines the time at which the output level go cross. v ol = 0.8 v, v oh = 2.0 v of output timing reference level. 23. before and after self refresh mode, execute cbr refresh to all refresh addresses in or within 64 ms period on the condition a and b below. a. enter self refresh mode within 15.6 m s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 m s after exiting from self refresh mode. 24. in case of entering from ras -only-refresh, it is necessary to execute cbr refresh before and after self refresh mode according as note 23. 25 at t rass > 100 m s, self refresh mode is activated, and not activated at t rass < 10 m s. it is undefined within the range of 10 m s t rass 100 m s. for t rass 3 10 m s, it is necessary to satisfy t rps . 26. when both ucas and lcas go low at the same time, all 16-bit data are written into the device. ucas and lcas cannot be staggered within the same write/read cycles. 27. t asc , t cah , t rcs , t wcs , t wch , t csr and t rpc are determined by the earlier falling edge of ucas or lcas . 28. t crp , t chr , t rch , t cpa and t cpw are determined by the later rising edge of ucas or lcas . 29. t cwl , t dh , t ds and t chs should be satisfied by both ucas and lcas . 30. t cp is determined by the time that both ucas and lcas are high. 31. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
HM5164165F series, hm5165165f series 18 notes concerning 2 cas control please do not separate the ucas / lcas operation timing intentionally. however skew between ucas / lcas are allowed under the following conditions. 1. each of the ucas / lcas should satisfy the timing specifications individually. 2. different operation mode for upper/lower byte is not allowed; such as following. ras ucas lcas we delayed write early write 3. closely separated upper/lower byte control is not allowed. however when the condition (t cp t ul ) is satisfied, edo page mode can be performed. ras ucas lcas t ul 4. byte control operation by remaining ucas or lcas high is guaranteed.
HM5164165F series, hm5165165f series 19 timing waveforms * 31 read cycle ras address we dout oe din t rc row column t rcs t rch t cdd t dzc high-z dout t dzo t oed t rac t oea t aa t cac t clz t oh t off t oho t oez ucas lcas t rdd t wed t ofr t ohr t wez t ras t cas t rp t csh t rcd t rsh t crp t t t rad t ral t cal t asr t asc t cah t rchr t rrh t rah
HM5164165F series, hm5165165f series 20 early write cycle ras address we din dout t rc * t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din t wcs wcs (min) high-z* t ucas lcas
HM5164165F series, hm5165165f series 21 delayed write cycle * 18 address ucas lcas ras we din oe dout t rc t ras t rp t csh t rcd t rsh t cas t crp t t column row t asr t rah t asc t cah t rcs t cwl t rwl t wp t dzc t ds t dh t dzo t oed t oeh t oep t clz t oez high-z invalid dout din high-z
HM5164165F series, hm5165165f series 22 read-modify-write cycle * 18 address ras din dout oe we t rwc t ras t rp t crp t cas t rcd t t t rad t asr t rah t asc t cah column row t rcs t cwd t cwl t awd t rwd t rwl t wp t dzc t dh t ds din high-z t dzo t oed t oeh t oea t cac t aa t rac t oho t oez t clz dout high-z ucas lcas t oep
HM5164165F series, hm5165165f series 23 ras -only refresh cycle ! ras ucas lcas address dout high-z row t rc t rp t ras t t t crp t rpc t crp t asr t rah t off t ofr
HM5164165F series, hm5165165f series 24 cas -before- ras refresh cycle ras ucas lcas we address dout high-z t off t ofr t wrp t wrh t wrp t wrh t cp t rpc t csr t chr t cp t rpc t csr t chr t crp t rp t ras t rc t rc t rp t ras t rp t t
HM5164165F series, hm5165165f series 25 hidden refresh cycle din oe dout we address ras t rc t rc t rc t rp t ras t rp t ras t rp t ras t t t rcd t rsh t chr t crp t rad t ral t cah t asc t rah t asr t cdd t dzc t oed t oez t oho t off t oh t cac t aa t rac t clz dout column row t oea high-z t rch t rrh ucas lcas t wed t rdd t wez t ofr t ohr t rcs t dzo
HM5164165F series, hm5165165f series 26 edo page mode read cycle
din oe dout we address ras ucas lcas t cp t cp t cp t t t rch t rrh t dzc t cdd t rdd high-z t ofr t oez t oho t off t oh t ohr t t col t oep t t cpa t aa t cac t cac t oea t aa t rac t aa t cac t cpa t t oez t oea t oez t aa t cac t t rasp cop t rp t cas t cas t cas t cal t csh t hpc t hpc crp t t asr t rah column 1 column 2 column 3 column 4 t t cah t asc t cah t cah t asc t cah t asc t wed t ral row dout 2 dout 2 dout 4 dout 1 t cas t rcs t t wpe dout 3 t oho t t cprh t hpc t oea t wez dzo t oed t oep oho doh rch t rcs t rchr t cal t cal t cal t rsh t rchc cpa asc
HM5164165F series, hm5165165f series 27 edo page mode read cycle (2 cas control) % oe we address t dzc t cdd t rdd high-z t ofr t oez t oho t off t oh t ohr t t col t t cpa t aa t cac t cac t oea t aa t rac t aa t doh t t oez t t oez t aa t cac t cop t oep t asr t rah column 1 column 2 column 3 column 4 t t cah t asc t cah t cah t asc t cah t asc t wed t ral row dout 2 dout 4 dout 1 t rcs t oho t oea dzo t oed t oep t cac t rchc cpa asc ras ucas lcas t cp t cp t cp t t t rch t rrh t rasp t rp t cas t cas t cas t csh t hpc t hpc t hpc crp t t cas t rsh l dout u dout dout 1 dout 3 dout 2 oho oea dout 4 t cpa t cal cal cal t t cal t din
HM5164165F series, hm5165165f series 28 edo page mode early write cycle * t wcs wcs (min) ras address we din dout t rasp t rp t t t csh t hpc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah t wch t wcs t wch t wcs t wch t wcs t dh t ds t dh t ds t dh t ds din 1 din 2 din n high-z* t row column 1 column 2 column n ucas lcas
HM5164165F series, hm5165165f series 29 edo page mode delayed write cycle * 18 ! " we din oe dout address ras t rasp t rp t crp t rsh t cas t hpc t cas t cas t csh t rcd t t t cp t cp t asc t cah t asc t cah t asc t cah t rad t asr t rah t rcs t rcs t rcs t rwl t cwl t cwl t cwl t wp t wp t wp t dzc t ds t dzc t ds t ds t dzc t dh t dh t dh t dzo t oed t dzo t oed t dzo t oed t oeh t oeh t oeh t oez t clz t clz t oez t clz t oez invalid dout invalid dout invalid dout din 1 din 2 din n column n column 2 column 1 row high-z ucas lcas t oep t oep t oep
HM5164165F series, hm5165165f series 30 edo page mode read-modify-write cycle * 18 "# )* we din oe dout address ras t rasp t crp t cp t hprwc t t t rcd t cas t cp t cas t cas t rad t asr t asc t asc t asc t rah t cah t cah t cah t cwl t cpw t cwl t cpw t cwl t rwd t awd t awd t awd t cwd t rcs t cwd t rcs t cwd t rcs t wp t wp t wp t ds t dzc t ds t dzc t ds t dzc t dh t dh t dh t dzo t dzo t dzo t oeh t oep t oep t oep t oeh t oeh t aa t rac t oez t clz dout n dout 2 dout 1 din 1 din 2 din n column n column 2 column 1 t rp row t rwl t oho t oea t cac t oez t clz t oho t oea t cac t cpa t oez t clz t oho t oea t cac t cpa high-z t oed t oed t oed aa t aa t t rsh ucas lcas
HM5164165F series, hm5165165f series 31 edo page mode mix cycle (1) * 20 oe dout we address ras lcas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t cpa t oez t aa t oea t t rasp t rp t cas t cas t cas crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t cah t ral t cal row dout 2 dout 4 cpa t cas t wcs dout 3 t t t wp t cwl t wch t wed t wez t ds t dh t ds t dh din 3 din 1 t oea t oed t oep t cac t asc t cpw t awd oho t cal t rcs t rcs t csh t rcd t rsh doh asc t din ucas
HM5164165F series, hm5165165f series 32 edo page mode mix cycle (2)* 20 din oe dout we address ras t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t oez t t oea t t rasp t rp t cas t cas t cas t csh crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t asc t cah t ral t rcs row dout 1 dout 4 cpa t cas t cwl dout 3 t oho t wed t wez t ds t dh t ds t din 3 din 2 t oea t t cac t cpw t rch t rcs t wch t rac t oed t col t oea t oho t oez t dh oed t rcs t cal t cal t rcd t rchr t wcs t rsh t wp t asc aa t oep t oep cop cas cas ucas lcas
HM5164165F series, hm5165165f series 33 self refresh cycle (l-version)* 23, 24, 25 $ % & + , ras dout t rp t rass t rps t rpc t t t cp t csr t chs t crp t off t ofr high-z ucas lcas t wrp t wrh we
HM5164165F series, hm5165165f series 34 package dimensions HM5164165Fj/flj series hm5165165fj/flj series (cp-50da) 20.95 21.38 max 50 26 125 0.47 10.16 0.13 11.18 0.13 3.50 0.26 9.40 0.25 1.09 max 0.90 0.26 2.55 0.12 0.30 0.04 *0.32 0.08 hitachi code jedec eiaj weight (reference value) cp-50da conforms 1.2 g unit: mm *dimension including the plating thickness base material dimension 0.10 0.80
HM5164165F series, hm5165165f series 35 HM5164165Ftt/fltt series hm5165165ftt/fltt series (ttp-50db) hitachi code jedec eiaj weight (reference value) ttp-50db 0.51 g unit: mm *dimension including the plating thickness base material dimension 0.13 m 0.10 0.80 50 26 125 20.95 21.35 max *0.30 1.20 max 10.16 0.13 0.05 11.76 0.20 0 ?5 1.15 max *0.145 0.05 0.28 0.05 0.125 0.04 0.50 0.10 0.68 0.80 + 0.10 ?0.05
HM5164165F series, hm5165165f series 36 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:
HM5164165F series, hm5165165f series 37 revision record rev. date contents of modification drawn by approved by 0.0 may. 25, 1999 initial issue m. kawamura m. mishima 1.0 oct. 5, 1999 features: change of power dissipation standby (l-version) max: tbd to 1.1 mw dc characteristics i cc2 (l-version) max: tbd/tbd to 300/300 m a i cc10 (l-version) max: tbd/tbd to 1/1 ma i cc11 (l-version) max: tbd/tbd to 500/500 m a m. kawamura y. kasama 2.0 nov. 30, 1999 dc characteristics i cc10 (l-version) max: 1/1 ma to 1.2/1.2 ma

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